1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device having a write leveling mode for measuring a skew between a clock signal and a data strobe signal. The present invention also relates to a module including this semiconductor device and to a data processing system.
2. Description of Related Art
Transmission and reception of read data and write data between a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) and a memory controller may be performed synchronously with a data strobe signal. For example, in a write operation, a memory controller supplies a data strobe signal and write data to a semiconductor memory device, and the semiconductor memory device fetches the write data synchronously with the data strobe signal.
However, the write data fetched by the semiconductor memory device is transferred to a memory cell array synchronously with a clock signal, which is different from the data strobe signal. Therefore, when a skew exists between the data strobe signal and the clock signal, a write operation cannot be performed correctly. To solve this problem, semiconductor memory devices often include a write leveling mode for measuring the skew between a clock signal and a data strobe signal (see JEDEC STANDARD, DDR3 SDRAM Specification, JESD79-3B (Revision of JESD79-3A, September 2007), April 2008, JEDEC SOLID STATE TECHNOLOGY ASSOCIATION <URL:http://www.jedec.org/download/search/JESD79-3B.pdf >).
Note that in the present application, the disclosure of the non-patent literature mentioned above is incorporated herein by reference.
Upon entering a write leveling mode, a semiconductor memory device samples a clock signal at a timing of a rising edge of a data strobe signal supplied from a memory controller, and outputs the sampled clock signal from a data terminal. With this configuration, the memory controller can acquire an amount of skew between the data strobe signal and the clock signal. Consequently, the memory controller can adjust an output timing of the data strobe signal by taking the amount into consideration.
Because the write leveling operation mentioned above is an operation of measuring a skew between a data strobe signal and a clock signal in a write operation, it is preferable to perform the operation in the same condition as that of an actual write operation as much as possible.
Meanwhile, some semiconductor memory devices have a so-called a dynamic ODT (On Die Termination) function. According to the dynamic ODT function, it becomes possible to change a resistance of a terminating resistance circuit incorporated in a semiconductor memory device dynamically, and to change a resistance of the terminating resistance circuit to different values between that when the semiconductor memory device performs a write operation and that when another semiconductor memory device connected to the same bus performs a read operation. Therefore, when the dynamic ODT function is active, the resistance of the terminating resistance circuit changes in response to issuance of a write command.
However, because any write command is not issued during a write leveling operation, the resistance of the terminating resistance circuit is not set as a resistance when the corresponding semiconductor memory device performs a write operation, but is set as a resistance when another semiconductor memory device connected to the same bus performs a read operation. Due to this, according to a conventional semiconductor memory device, when the dynamic ODT function is active, the resistance of the terminating resistance circuit at the time of write leveling is different from that at the time of the write operation, and thus an accurate write leveling operation cannot be performed.